Date of Award
1-1-2023
Document Type
Dissertation
Degree Name
Ph.D. in Engineering Science
First Advisor
Md Sakib Hasan
Second Advisor
Ramanarayanan Viswanathan
Third Advisor
Kasem Khalil
School
University of Mississippi
Relational Format
dissertation/thesis
Abstract
This document presents a Ph.D. dissertation that focuses on designing overhead constrained circuits for chaos-based hardware security applications in integrated circuit (IC) technology. The designed circuits are optimized for promising chaotic behavior while maintaining the constrained area, delay, and power budget. This research includes proposing novel circuit topologies for attaining superior chaotic complexity, analyzing chaotic performance with multiple metrics, proposing the designs for real-world hardware-security applications that leverage proposed circuit topologies, and analyzing the security aspects of the designed applications. Multiple circuit design techniques are presented in this document. All the proposed works fall under the central motivation of designing low area, low-power, and high-speed chaos-generating circuits that are suitable for chaos-based hardware security applications in the IC environment. Propositions are discussed with the design motivation, the general framework of the design, design implementation for Cadence-based simulation, evaluation of chaotic performance, and the analysis of circuit overhead cost. Applications of the proposed topologies in the real-world hardware security protocol are discussed, as well. It is demonstrated that the proposed circuit topologies are suitable to implement chaos-based hardware security protocols for overhead constrained IC applications.
Recommended Citation
Paul, Partha Sarathi, "Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits" (2023). Electronic Theses and Dissertations. 2708.
https://egrove.olemiss.edu/etd/2708