Date of Award
1-1-2023
Document Type
Dissertation
Degree Name
Ph.D. in Engineering Science
First Advisor
Lei Cao
Second Advisor
Md Sakib Hasan
Third Advisor
Kaseem Khalil
School
University of Mississippi
Relational Format
dissertation/thesis
Abstract
Rapid advancement in technology has led to an increase in security threats, such as side-channel attacks and reverse engineering, which can potentially leak sensitive data or code to malicious parties. To address these challenges, researchers harness the inherent complexity of chaos-based computing. Leveraging chaos offers several advantages, including logic obfuscation, mitigation of power analysis attacks, and encryption of images and data.
The motivation has been to design hardware-efficient circuits that meet modern systems’ power, area, and performance requirements and provide enhanced security. We have introduced our novel one-dimensional discrete chaotic map circuits, designed using a 45nm CMOS process, although the proposed topologies are applicable across different technology nodes. The key advantage of these designs lies in their hardware efficiency, achieved by utilizing only four MOS transistors. Despite their simple design, these circuits exhibit robust chaotic performance over a wide range of chaotic parameters. We analyzed the circuit’s chaotic performance using various entropy metrics, such as bifurcation plot, Lyapunov exponent, correlation coefficient, sample entropy, and Shannon entropy. The results demonstrate significant improvement over previous transistor-level designs and highlight the excellent properties of randomness across a wide chaotic parameter range.
Additionally, four novel chaotic maps based on silicon-on-insulator (SOI) technology are also reported. Two of these maps utilize a G4FET configuration with two p-channel and one n-channel SOI four-gate transistors, while the other two designs employ two n-channel and one p-channel G4FET configuration. The unique multi-gate structure of G4FET provides four independent bifurcation parameters. Furthermore, the application of a multi-parameter chaotic oscillator in a chaos-based reconfigurable logic gate is also explored. The availability of multiple bifurcation parameters offers a significant improvement in the functionality space. This enhances the flexibility and versatility of the system leading to a wide range of configurations.
A significant expansion of parameter design space compared to existing maps is demonstrated by proposing a simple extension scheme to develop multi-dimensional robust chaotic maps. The scheme allows for the exploration of higher-dimensional maps by utilizing additional control parameters. This approach is verified using 2-D and 3-D schemes. Finally, the future direction of research is also discussed.
Recommended Citation
Sadia, Maisha, "Design and Application of Single and Multi-Gate Transistor-Based Analog Chaotic Maps" (2023). Electronic Theses and Dissertations. 2720.
https://egrove.olemiss.edu/etd/2720