Date of Award
1-1-2024
Document Type
Thesis
Degree Name
M.S. in Engineering Science
First Advisor
Kasem Khalil
Second Advisor
Azeemuddin Syed
Third Advisor
Md Sakib Hasan
Relational Format
dissertation/thesis
Abstract
Artificial intelligence (AI) hardware accelerator is an emerging research for several applications and domains. The hardware accelerator aims to provide high computational speed while retaining low cost and high learning performance. The main challenge is to design complex machine learning models on hardware with high performance. In this thesis, the aim is to develop the hardware implementation of perceptron within a neural network. Innovative hardware-based approaches are explored to optimize perceptron networks, enhancing accuracy, reliability, and fault tolerance while minimizing resource requirements and power consumption.
A thorough investigation into machine learning accelerators and associated challenges was initially conducted. The hardware implementation of different structures such as Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), and Artificial Neural Network (ANN) was described. The challenges such as speed, area, resource consumption, and throughput were discussed. A comparison between the existing hardware design was also presented. Additionally, the evaluation parameters for a machine learning accelerator in terms of learning and testing performance, and hardware designs were described.
Subsequently, a novel approach to perceptrons was proposed by incorporating a feedback mechanism using a gain factor, replacing conventional learning rates. The proposed method aimed to optimize network performance while adapting to hardware constraints. Implementing MNIST and Heart Attack datasets showcased the superiority of the proposed approach over traditional methods, revealing substantial accuracy improvements across various activation functions (Sign, Step, and Sigmoid) in both single perceptron and multilayer perceptron (MLP) architectures. The proposed methods have been implemented and evaluated on FPGA platforms. The proposed method demonstrated remarkable accuracy enhancements in pattern recognition tasks, promising advancements in real-world applications.
Lastly, the concept of self-healing in Neural Networks was explored, empowering systems to detect and recover from faults. The focus was on a novel self-healing approach for hardware neural networks, employing a shared mechanism and a spare layer to address faulty perceptron nodes. The fault detection method centered on Stuck-at-fault detection, is crucial for identifying and subsequently recovering faults within the network. The proposed self-healing perceptron operated in two modes: healing and regular, facilitating fault recovery while minimizing area overhead. The proposed method was implemented using VHDL and the simulation obtained using Xilinx Virtex-7 FPGA showcased promising results, demonstrating reduced area overhead with increased network complexity. Reliability analysis illustrated the proposed method’s effectiveness in ensuring seamless functionality over time compared to traditional approaches.
Overall, the findings presented in this thesis contributed to the ongoing development of efficient and robust artificial intelligence hardware accelerators, with potential applications spanning diverse domains such as pattern recognition, data analysis, and real-time processing. Future research directions involved further optimization of hardware implementations of feedback perceptron approach, exploration of additional self-healing mechanisms, and validation of proposed methods across a broader range of applications and datasets.
Recommended Citation
Mohaidat, Tamador Nadem, "Efficient Design of Neural Network Hardware Accelerator for Enhanced Performance in Deep Learning Systems" (2024). Electronic Theses and Dissertations. 2843.
https://egrove.olemiss.edu/etd/2843